The present invention relates generally to a semiconductor memory device, and more particularly to a semiconductor memory device including a reset control circuit which controls the reset of an internal circuit.
A reset signal is inputted into a semiconductor memory device to initialize circuit having an operation previously set so as to provide normal operation of an internal circuit of the semiconductor memory device. That is, after the semiconductor memory device is initialized by the reset signal, the semiconductor memory device inputs and outputs data according to a setting of a mode register set and an inputted command.
The semiconductor memory device receives the reset signal from the outside to initialize the data and maintains the initialization state as the reset signal maintains an enablement state for predetermined time. Thereafter, the reset signal is disabled and the command is input, such that the data have a valid value according to the command.
However, during high frequency operation of the semiconductor memory device a significant amount of noise is generated, and as a level of an operation voltage is decreased, a probability of a generation of a glitch in the reset signal is increased.
When the glitch is generated in the reset signal, the glitch causes the reset signal to be instantly enabled, such that the data output may have the initialized value as opposed to the valid data. That is, although the command is input after the glitch occurs in the reset signal, the data maintain the initial value because of the glitch. This results in a problem in that the data value according to the command cannot be processed normally.
This semiconductor memory device cannot determine whether the reset signal is properly enabled to initialize the internal circuit, or enabled due to the glitch. Therefore, there is a problem associated with the semiconductor memory device as described above in that the occurrence of the glitch in the reset signal may result in device malfunction.